For switching mechanisms generally and data transmission systems in particular, clock frequencies are required for the active components. They are generated by phase-locked loops, for example, which are known by the designation “PLL”. Such a PLL operating in analog fashion is described for example by Dr. Roland Best in “Theorie und Anwendungen des Phase-locked Loops” [“Theory and applications of the phase-locked loop”], 1987, ISBN 3-85502-132-5.
A PLL is accordingly a regulating system which is used to synchronize the output signal of an oscillator (local clock signal) with an input signal in terms of frequency and phase. In the synchronized state of the PLL, the phase shift between the input signal and the output signal of the oscillator is intended to be minimal and as far as possible to tend toward zero. As soon as a phase shift occurs between the two signals, the oscillator is readjusted until the phase shift is zero or minimal again. Voltage-controlled oscillators (VCO) and current-controlled oscillators (CCO) are known. The PLL includes a phase detector and a loop filter alongside the oscillator.
A PLL operates without significant problems in analog systems. However, corresponding circuits are relatively complex, having many individual parts and a correspondingly large space requirement. Therefore, digital systems of simpler construction have been developed and are commercially available, but difficulties can occur in these systems since there are regions in which the phase detector does not supply information about the phase deviation between the two signals to be compared. The processing of digital datastreams in receiving circuits is disturbed as a result. Incorrect sampling can occur.
The known method according to EP 1 032 133 A1 mentioned in the introduction uses a PLL which has a small phase error, such that incorrect sampling can be precluded to the greatest possible extent. It has a digital phase detector, a digital loop filter connected to the latter, and a digital/analog converter connected to the latter, to all of which a common clock signal is applied. A quartz-stable, controllable oscillator is connected to the output of the digital/analog converter, which oscillator generates a local clock signal corresponding to the clock frequency to be regulated, said clock frequency being dependent on a reference clock signal, as output signal. The phase detector is fed the reference clock signal as first input signal via a first input and the local clock signal as second input signal via a second input. The relative phase angle of the two clock signals is ascertained in phase detector by means of sampling pulses whose spacing from one another is determined by the common clock signal. Upstream of one of the inputs of the phase detector, a multiplexer is connected into the transmission path of the respective incoming input signal, to which the corresponding input signal is fed directly, on the one hand, and via a delay circuit, on the other hand, and by which the reference clock signal or the local clock signal is fed to the phase detector either directly or in delayed fashion. The phase detector samples the phase angle of the two clock signals alternately shortly before and shortly after the respective edge. Incorrect sampling nevertheless cannot be precluded in case of this method either.